(A) Field of the Invention
The present invention is related to a circuit and a method for preventing over-erase of memory, which are specifically applied to a nonvolatile memory.
(B) Description of the Related Art
Nonvolatile memory, especially NOR flash memory, often suffers the problem of over-erase. In general, a chip is made up of cell arrays connected to each other by means of a plurality of wordlines and bitlines arranged in rows and columns. For example, a bitline links the drains of 512 cells. The erasing of a cell is accompanied by that of the other cells. In a situation where cells at a certain address are not fully erased, erasing will take place continuously and repeatedly unless and until it is done. As a result, cells which are readily erased may be over-erased. The cells can cause leakage current to the bitlines they belong to, if over-erased, and in consequence an accumulation of excessive leakage current leads to a faulty reading, writing or over-erase correction. For instance, the state of programmed cells is mistaken for the state of erased cells, or excessive supplying current is needed during programming and over-erase correction. These problems are particularly serious in an environment where the supplying current is low or the temperature is high. Normal cells have their erasing verification compared with erasing reference cells in order to be erased, their programming verification compared with programming reference cells in order to be programmed, and their reading verification compared with reading reference cells in order to be read. There can be only one reference cell whose wordline voltage is set to different verification-dependent values in order to supply different reference cell currents for the sake of comparison.
Generally, every nonvolatile memory cell comprises a control gate and a floating gate. If the capacitance of the tunnel oxide layer of the cell is denoted by Cox and the dielectric layer such as ONO, that is, a multi-layer composed of an oxide layer, a nitride layer and an oxide layer, between the floating gate and the control gate is denoted by CONO, then the coupling factor is expressed as CONO/(CONO+COX). The higher the coupling factor is, the greater the proportion of the voltage applied to the control gate coupled to the floating gate is.
FIG. 1 shows the relationship between the threshold voltage Vt for erasing cells of different coupling factors and time, wherein the numerical value in the bracket behind Vt refers to a coupling factor. The higher a coupling factor is, the more efficient the voltage coupled to a floating gate is, so its corresponding threshold voltage Vt drops faster. For instance, when the threshold voltage of a cell with a coupling factor of 0.56 is erased to about 3V, the threshold voltage of a cell having the coupling factor of 0.68 is already decreased to 0.4V. Therefore, the cell with the coupling factor of 0.68 is very likely to generate leakage current due to the low threshold voltage or contribute a punch-through between the source and the drain. The aforesaid current leakage problem is quite common, because the coupling factor of each cell varies and it depends on the cell structure design and the manufacturing processing of the chips.
FIGS. 2 and 3 are diagrams depicting the current vs. voltage characteristics of a single cell at temperatures of 85° C. and 25° C., respectively. The abscissa plots control gate voltage, whereas the ordinate plots current flowing from the drain to the source. In addition, a voltage of 1V is applied to the drain, and the source is grounded.
Referring to FIG. 2, three curves are plotted under different threshold voltages, namely 0.25V, 1.07V and 2.9V respectively. And these Vt are defined at 25° C. If Vt is 1.07V and wordline voltage is 0.45V, which is what happens at point A, the cell creates a current of approximately 20 nA. If point A is transversely shifted to point B, which is under a zero voltage, and the 20 nA current remains unchanged, Vt, which corresponds to point B, becomes approximately 0.62V. As a result, if a cell has a threshold voltage of 0.62V, even though zero voltage is applied to a wordline, a leakage current of around 20 nA is still generated. Consequently, in the case of a bitline comprising 512 bits, i.e., comprising 512 cells, the bitline will create a leakage current of approximately 10 μA (20 nA×512).
Referring to FIG. 3, under the circumstance of 25° C., point D, which similarly contributes a 20 nA leakage current in the cell, has a corresponding threshold voltage of approximately 0.42V. Referring to FIG. 2 again, in the case of the threshold voltage of 0.42V and under the circumstance of 85° C., which is what happens at point C, the corresponding leakage current is approximately 116 nA, and therefore the whole bit line accounts for a leakage current of 58 μA. A summary of the aforesaid findings is found in Table 1.
TABLE 1WordlineBitline LeakageVt at 25° C.TemperatureVoltageCurrentCurrent (512 cells)1.07 V85° C.0.45V20nA10 μA0.62 V85° C.0V20nA10 μA0.42 V25° C.0V20nA10 μA0.42 V85° C.0V116nA58 μA
This shows that, even if erase operations are smoothly carried out on cells that are hard to be erased at low temperature, it is likely that leakage current increases at high temperature and causes a false reading. Threshold voltage Vt depends on the design of cells as well as the consideration given to varying degrees of reliability and speed. At present, prevention of over-erase is mostly achieved by improving erase algorithms, but over-erase may occur in the presence of a faulty erase algorithm.
U.S. Pat. No. 6,157,572, No. 6,285,599, No. 6,172,915, No. 5,414,664, No. 5,856,945, No. 6,529,413, No. 6,314,027, No. 6,188,609, No. 5,642,311, No. 6,567,316, No. 6,490,203, No. 5,544,116 and No. 4,875,188 disclose methods for preventing the over-erase of nonvolatile memory. However, they fail to solve the over-erase problem which arises because a coupling factor varies from process deviation.